Additive Lithography - Organic Monolayer Patterning Coupled with an Area-Selective Deposition
- Rudy Wojtecki
- Jonathan Ma
- et al.
- 2021
- ACS AMI
Nick Lanzillo
Title
Research Staff Member
Bio
Nick earned a B.S. in physics from Syracuse University and a Ph.D. in physics from Rensselaer Polytechnic Institute (RPI) in Troy, NY. He joined IBM in 2016 as part of the back-end-of-line (BEOL) integration team and currently works on leading edge technology development with a focus on design-technology co-optimization (DTCO.) Nick was named an IBM Master Inventor in 2020 and again in 2023. He currently serves on the committee for the IEEE International Interconnect Technology Conference.
Publications
Interconnect scaling challenges, and opportunities to enable system-level performance beyond 30 nm pitch
- Griselda Bonilla
- Nicholas A. Lanzillo
- et al.
- 2020
- IEDM 2020
Topological semimetals for scaled back-end-of-line interconnect beyond Cu
- Ching-Tzu Chen
- Utkarsh Bajpai
- et al.
- 2020
- IEDM 2020
Comprehensive BEOL Performance Assessment: Interconnects Optimized for Signal Routing and Power Delivery in Advanced CMOS Technology Nodes (Invited)
- Nicholas A. Lanzillo
- Rwik Sengupta
- et al.
- 2020
- IITC 2020
Role of high aspect-ratio thin-film metal deposition in Cu back-end-of-line technology
- Andrew Simon
- O. Van Der Straten
- et al.
- 2020
- JVSTA
Composite Interconnects for High-Performance Computing beyond the 7nm Node
- P. Bhosale
- S. Parikh
- et al.
- 2020
- VLSI Technology 2020
First-Principles Evaluation of fcc Ruthenium for its use in Advanced Interconnects
- Timothy M. Philip
- Nicholas A. Lanzillo
- et al.
- 2020
- Physical Review Applied
Structural and transport properties of Cu/Ta(N)/Cu interfaces in vertical interconnects
- Nicholas A. Lanzillo
- Lawrence Clevenger
- et al.
- 2020
- Journal of Applied Physics
Surface initiated polymer thin films for the area selective deposition and etching of metal oxides
- Thomas G. Pattison
- Alexander E. Hess
- et al.
- 2020
- ACS Nano
Chip Power-Frequency Scaling in 10/7nm Node
- Phil Oldiges
- Reinaldo A. Vega
- et al.
- 2020
- IEEE Access
Patents
- US
- 10319629
- US
- 10256191
- US
- 10243020
- US
- 10211155
- US
- 9985199
- US
- 9941211
Top collaborators
DD
Dan J. Dechene
Director, Semiconductor Enablement
HB
Huiming Bu
Vice President: IBM Semiconductors Global R&D and Albany Operations
TY
Tenko Yamashita
Senior Manager - Advanced Logic Pathfinding Technology
HH
Huai Huang
BEOL Reliability, Quality and Characterization