Logic Technology
Designing the next generation of chips to increase performance and improve energy efficiency.
Logic scaling is the pathway to advance semiconductor technology to smaller components, to increase performance or to improve energy efficiency. We achieve logic scaling through advances in chip technology such as new architectures and new materials, driving breakthroughs in transistor and interconnect technology at the atomic scale. Our materials and architectures move the industry forward, to meet the world’s demand for increasingly powerful and energy efficient chips.
For decades, IBM has led the industry in logic scaling technology. We coined the term “Nanosheet” in 2015 and, more recently, unveiled our 2 nanometer node test chip in 2021. From approaching 1 nanometer components to scaling foundational technology, our work in logic technology is accelerating the progress and productivity of the chip industry, in collaboration with a rich ecosystem of partners based in Albany, NY. Learn more about IBM Research Albany
Our work
Why we need EUV lithography for the future of chips
ExplainerMike MurphyThe path to 1 nanometer chips and beyond
ResearchMike MurphyThe future of computer chips is being built in Albany
Deep DiveMike MurphyVTFET: The revolutionary new chip architecture that could keep Moore’s Law alive for years to come
NewsBrent Anderson and Hemanth Jagannathan5 minute readIntroducing the world's first 2 nm node chip
NewsJulien Frougier and Dechao Guo5 minute readEUV patterning yield breakthrough sets new benchmark for logic scaling
Technical noteNelson Felix and Luciana Meli4 minute read- See more of our work on Logic Technology
Publications
Critical Elements for Next Generation High Performance Computing Nanosheet Technology
- R. Bao
- C. Durfee
- et al.
- 2021
- IEDM 2021
Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- Ruqiang Bao
- Yusuke Oniki
- et al.
- 2024
- IEDM 2024
Small Signal Capacitance in Ferroelectric HZO: Mechanisms and Physical Insights
- Revanth Kodoru
- Atanu Saha
- et al.
- 2024
- arXiv
DTCO Guided Process Integration: Case Studies From FEOL & BEOL with BSPDN
- Minhaz Abedin
- Shahrukh Khan
- et al.
- 2024
- ASMC 2024
Topological Semimetal Resistivity Scaling for Vertical Interconnect Applications
- Nick Lanzillo
- Utkarsh Bajpai
- et al.
- 2024
- Applied Physics Letters
New Approach of LCDU Improvement for Via/Contact Hole Etch at Cryogenic Temperature
- Emilia Hirsch
- Dominik Metzler
- et al.
- 2024
- JVSTB
Projects
Platform technology research: innovation and solution creation for leading edge CMOS technology at 2nm node.