Evaluating Novel Material Stacks Towards Gate Width Roughness Reduction
- Gopal Kenath
- Martin Burkhardt
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
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15 results for Logic Scaling
Accelerating High NA EUV Lithography Insertion for Interconnect Scaling and Beyond: Performance, Cost, and Future Prospects
- Luciana Meli
- Indira Seshadri
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
- Topic
Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- Ruqiang Bao
- Yusuke Oniki
- et al.
- 2024
- IEDM 2024
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- Shogo Mochizuki
- Nicolas Loubet
- et al.
- 2023
- IEDM 2023
LogInsights: Understanding and Extracting Information from Logs for Fast Fault Classification by Weak Supervision
- Suranjana Samanta
- Prateeti Mohapatra
- et al.
- 2023
- SSE 2023
A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology
- N. Jungmann
- Rajiv V. Joshi
- et al.
- 2023
- VLSI Technology 2023
TSV Stress Evolution Mapping using in-line Raman Spectroscopy
- Stefan Schoeche
- Daniel Schmidt
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Dry Resist Characterization Towards Technology Insertion for 28-36P EUV Patterning
- Yasiel Cabrera
- Gopal Kenath
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
DTCO Guided Process Integration: Case Studies From FEOL & BEOL with BSPDN
- Minhaz Abedin
- Shahrukh Khan
- et al.
- 2024
- ASMC 2024