Optimization of 3nm High Performance Nanosheet Technology for 77 K Operation
- Julien Frougier
- Ruqiang Bao
- et al.
- 2025
- GOMACTech 2025
Julien Frougier
Title
Senior Engineer: IBM Semiconductors - Advanced Logic Technology Research
Publications
Novel ellipsometry-based machine learning technique for characterization of low sensitivity critical dimensions within gate-all-around transistors
- Houssam Chouaib
- Valeria Dimastrodonato
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Scaling opportunities for Gate-All-Around and beyond: A patterning perspective
- Indira Seshadri
- Eric Miller
- et al.
- 2023
- IEDM 2023
Development of SiGe Indentation Process Control for Gate-All-Around FET Technology Enablement
- Daniel Schmidt
- Aron Cepler
- et al.
- 2022
- IEEE Trans Semicond Manuf
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Subhadeep Kal
- et al.
- 2021
- ECS Meeting 2021
Nanosheet Metrology Opportunities for Technology Readiness
- Mary Breton
- Daniel Schmidt
- et al.
- 2021
- SPIE Advanced Lithography 2021
Patents
- US
- 12255651
- US
- 12256554
- US
- 12249643
- US
- 12245517
- US
- 12224312
- GB
- 2607481
- US
- 12211848
- KR
- 10-2753841
- US
- 12183740
- US
- 12176345
Projects
Platform technology research: innovation and solution creation for leading edge CMOS technology at 2nm node.
Blog posts
Introducing the world's first 2 nm node chip
NewsJulien Frougier and Dechao Guo5 minute read
Top collaborators
DG
Dechao Guo
Director, Advanced Logic Technology R&D
HB
Huiming Bu
Vice President: IBM Semiconductors Global R&D and Albany Operations
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Nicolas Loubet
STSM, Advanced Logic Technology Research
MW
Miaomiao Wang
Manager, Reliability