Huiming Bu

Overview

Title

Vice President: IBM Semiconductors Global R&D and Albany Operations

Location

IBM Research - Albany Albany, NY USA

Bio

Dr. Huiming Bu is responsible for IBM global Semiconductor R&D strategy across world-wide labs. He oversees R&D activities in advanced logic, chiplet and advanced packaging, emerging memory and analog AI hardware at IBM Research. In addition to leading semiconductor technology R&D agenda, Huiming is also responsible for IBM Research Albany Lab site and fab operations.

Huiming has ~20 years of professional experience in semiconductor technology R&D at IBM after he received his Ph.D. in Electrical Engineering from Yale University. Huiming has authored/co-authored 100+ technical publications and holds 100+ patents in semiconductor domain.

Huiming started his technical career at IBM on High-κ/Metal Gate project and then led SOI FinFET research and early development for IBM’s 14nm node technology. After that, Huiming and his team delivered 10nm/7nm technology R&D for IBM and its Joint Development Alliance (JDA) partners. They are now working on 2nm development and 1nm & beyond pathfinding R&D. Recently, as IBM formed Semiconductors division under IBM Research, the footprint has expanded from advanced logic to chiplet & advanced packaging, intelligent fab, cloud based EDA and design.

Publications

Backside power distribution for nanosheet technologies beyond 2nm
- - Ruilong Xie
  - Wonhyuk Hong
  - et al.
- 2024
- VLSI Technology and Circuits 2024
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- - Shogo Mochizuki
  - Nicolas Loubet
  - et al.
- 2023
- IEDM 2023
Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era
- - Hemanth Jagannathan
  - Susan Fan
  - et al.
- 2023
- SSDM 2023
The future transistors
- - Wei Cao
  - Huiming Bu
  - et al.
- 2023
- Nature
Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- - Biswanath (Biswa) Senapati
  - Jeongho Do
  - et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- - Gen Tsutsui
  - Seunghyun Song
  - et al.
- 2022
- IEDM 2022
Critical Elements for Next Generation High Performance Computing Nanosheet Technology
- - R. Bao
  - C. Durfee
  - et al.
- 2021
- IEDM 2021
Gate-Last IO Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies
- - M. Bhuiyan
  - M. Kim
  - et al.
- 2021
- IEDM 2021
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- - H. Jagannathan
  - B. Anderson
  - et al.
- 2021
- IEDM 2021
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
- - Curtis Durfee
  - Subhadeep Kal
  - et al.
- 2021
- ECS Meeting 2021

Patents

- 31 Oct 2023
- TW
- I821132
Self-aligned Backside Contact With Increased Contact Area
- 09 May 2022
- US
- 11329136
Enabling Anneal For Reliability Improvement And Multi-vt With Interfacial Layer Regrowth Suppression
- 04 Oct 2021
- US
- 11139385
Interface-less Contacts To Source/drain Regions And Gate Electrode Over Active Portion Of Device
- 09 Aug 2021
- US
- 11088278
Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers
- 17 May 2021
- US
- 11011513
Integrating A Junction Field Effect Transistor Into A Vertical Field Effect Transistor
- 01 Mar 2021
- US
- 10937867
Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices
- 11 Jan 2021
- US
- 10892181
Semiconductor Device With Mitigated Local Layout Effects
- 19 Oct 2020
- US
- 10811528
Two Step Fin Etch And Reveal For Vtfets And High Breakdown Ldvtfets
- 17 Aug 2020
- US
- 10748893
Electrostatic Discharge Devices And Methods Of Manufacture
- 10 Aug 2020
- US
- 10741647
Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices

Top collaborators

Huiming Bu

Overview

Title

Location

Bio

Publications

Backside power distribution for nanosheet technologies beyond 2nm

Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology

Vertical-Transport Nanosheet Technology for Scaling beyond the Lateral-Transport Devices CMOS Era

The future transistors

Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets

Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology

Critical Elements for Next Generation High Performance Computing Nanosheet Technology

Gate-Last IO Transistors based on Stacked Gate-All-Around Nanosheet Architecture for Advanced Logic Technologies

Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors

Patents

Self-aligned Backside Contact With Increased Contact Area

Enabling Anneal For Reliability Improvement And Multi-vt With Interfacial Layer Regrowth Suppression

Interface-less Contacts To Source/drain Regions And Gate Electrode Over Active Portion Of Device

Precise Junction Placement In Vertical Semiconductor Devices Using Etch Stop Layers

Integrating A Junction Field Effect Transistor Into A Vertical Field Effect Transistor

Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices

Semiconductor Device With Mitigated Local Layout Effects

Two Step Fin Etch And Reveal For Vtfets And High Breakdown Ldvtfets

Electrostatic Discharge Devices And Methods Of Manufacture

Conformal Doping For Punch Through Stopper In Fin Field Effect Transistor Devices

Top collaborators

Dechao Guo

Hemanth Jagannathan

Miaomiao Wang

Dan J. Dechene