Hemanth Jagannathan

Hemanth Jagannathan is a Distinguished Engineer at IBM. He has driven key technical advancements over several generations of semiconductor technologies ranging from planar, FinFET to Nanosheet and beyond nanosheet device architectures. Hemanth is currently the technical executive responsible for Chiplet and Advanced Packaging Technology at IBM Research. He received his Ph.D. in Electrical Engineering from Stanford University and began his technical career at IBM working on high-k metal gate technology. He drove multiple innovations on novel gate stack materials and processes that are being used to this day in advanced CMOS logic technologies. Hemanth also led the advanced semiconductor FEOL process technology team and was responsible in defining the comprehensive semiconductor process strategy for beyond planar, FinFET, Nanosheet and future device architectures. He was the Hardware Technologist who spearheaded the innovations for the Vertical-Transport Nanosheet Field Effect Transistor (VTFET) program at IBM.

Hemanth serves as an IBM representative in multiple academic engagements across the US. He is the executive director for the SUNY-IBM Artificial Intelligence Collaborative Research Alliance where he oversees joint AI research ranging from hardware, algorithms to software and applications. Hemanth is the recipient of multiple IBM Outstanding Technical Achievement Awards and Research Division Awards for his technical accomplishments. He is a senior member at IEEE and has authored/co-authored over 100 technical publications and holds over 200 patents in the semiconductor area.