Monolithic Stacked FET with Stepped Channels for Future Logic Technologies

Abstract

We present a monolithic stacked FET architecture featuring a stepped channel structure where the bottom FET channels are wider than the top. Such a design relieves high aspect ratio process challenges by reducing the total stack height and provides better performance as compared to its uniform channel width counterpart at the same footprint. In addition to the stepped channels, our integrated hardware work features top-bottom channel middle dielectric isolation, top-bottom source/drain isolation and dual work function metals. As the advanced technologies are facing significant power, performance and area scaling pressures, this work extends the narrowing road beyond the nanosheet architecture.