Composite Interconnects for High-Performance Computing beyond the 7nm Node

Abstract

We demonstrate a design-technology co-optimization (DTCO) solution for enabling novel composite interconnects in next-generation high-performance computing (HPC) applications. Minimum-pitch signal line optimization with aggressively shrunk feature size potentially requires a non-Cu conductor while relaxed-pitch signal and power line optimization require traditional Cu metallization, along with properly tuned power tap spacing, activity factor and standard cell size. We discuss significant process innovation required to co-optimize signal and power line resistances. Our composite metallization scheme also reduces via resistance by 50%, which results in a net performance uplift of between 2%-10% depending on via density and power requirements. We believe this is an optimal approach for HPC applications that have implemented alternate, higher-resistivity conductor metals at the 1x levels