Benchmarking Power Delivery Network Designs at the 5-nm Technology Node

Abstract

We evaluate a total of 96 different power delivery designs for a 5-nm node FinFET CMOS technology using eight levels of interconnect wiring. Our methodology considers the impact of a given design on the gate delay of an inverter as a figure of merit, while highlighting the tradeoff between power grid density and signal track density. Our design space includes designs with variable power line pitch at multiple levels of interconnect wiring as well as designs with continuous power rails replaced with power staples, covering both low-power and high-performance design points. We also evaluate the impact of the proposed technology features, such as skip-level vias and wafer front-side power rail removal. This work demonstrates the importance of power delivery design in advanced technology nodes and proposes a useful methodology for benchmarking designs as well as technology elements early on in a technology development cycle, ahead of more involved analysis such as plane-and-route.