Capacitive Impacts of Etch-Induced Dielectric Damage in Highly-Scaled Interconnect Architectures

Abstract

The effects of dielectric constant, damage layer thickness, line aspect ratio, and linewidth ratio on Back-End-of-Line (BEOL) line capacitance are evaluated for line pitches down to 18nm using field-solver simulations. At fine pitches such as 18nm, the damage layer thickness becomes increasingly important. We demonstrate when it may be beneficial to choose a higher-dielectric-constant material which does not create a damage layer, over a somewhat lower-dielectric-constant material. We also show the capacitive effects of metal aspect ratio, and metal width ratio, on 18nm-pitch wires.