Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes

Abstract

We assess the performance impact of cobalt interconnect metallization for both signal routing and power delivery in advanced logic technologies with a minimum metal pitch of 32 nm or less. While cobalt interconnects may enable lower line resistance in narrow signal lines than industry-standard copper interconnects below a threshold pitch, there is still a significant performance penalty associated with using cobalt in wide lines, including both signal and power. For wide signal lines at minimum-pitch metallization levels, we find a delay penalty as much as 60%-100% depending on signal run length for Co interconnects. For wide power lines at minimum-pitch metallization levels, we find a parasitic voltage (IR) drop penalty as high as 50% for Co interconnects. In light of these performance disadvantages, we discuss several design strategies to minimize the impact of Co metallization for both signal routing and power delivery. We also highlight critical differences between low-power and high-performance design points for power delivery.