Nelson Felix

Title

Director, Technical Business Development - IBM Semiconductors

Publications

EUV patterned gate variation reduction in next generation transistor architectures
- - Gopal Kenath
  - Martin Burkhardt
  - et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- - Shogo Mochizuki
  - Nicolas Loubet
  - et al.
- 2023
- IEDM 2023
Scaling opportunities for Gate-All-Around: A patterning perspective
- - I. Seshadri
  - E. Miller
  - et al.
- 2023
- IEDM 2023
Scaling opportunities for Gate-All-Around and beyond: A patterning perspective
- - Indira Seshadri
  - Eric Miller
  - et al.
- 2023
- IEDM 2023
Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors
- - Curtis Durfee
  - Ivo Otto
  - et al.
- 2023
- ECS Meeting 2023
Epi Source/Drain Damage Mitigation with Inner Spacer and Buffer Optimization in Stacked Nanosheet Gate-All-Around Transistors
- - Curtis Durfee
  - Ivo Otto
  - et al.
- 2023
- SSDM 2023
Advanced BEOL Materials, Processes, and Integration to Reduce Line Resistance of Damascene Cu, Co, and Subtractive Ru Interconnects
- - Takeshi Nogami
  - Oleg Gluschenkov
  - et al.
- 2022
- VLSI Technology and Circuits 2022
Etch and Patterning Development for 2nm Node Nanosheet Devices
- - Eric Miller
  - Indira Seshadri
  - et al.
- 2022
- SPIE Advanced Lithography 2022
Review of nanosheet metrology opportunities for technology readiness
- - Mary A. Breton
  - Daniel Schmidt
  - et al.
- 2022
- JM3
EUV single exposure via patterning at aggressive pitch
- - Jing Guo
  - Jennifer Church
  - et al.
- 2021
- SPIE Advanced Lithography 2021

Visit Google Scholar

Patents

- 30 Sep 2014
- US
- 8847416
Multi-layer Chip Overlay Target And Measurement
- 28 Jan 2014
- US
- 8638438
Self-calibrated Alignment And Overlay Target And Measurement
- 29 Jan 2013
- US
- 8361683
Multi-layer Chip Overlay Target And Measurement

Blog posts

IBM and Albany partners unlock new yield benchmarks for EUV patterning
Technical note
Luciana Meli and Nelson Felix
24 Oct 2024
- Semiconductors
EUV patterning yield breakthrough sets new benchmark for logic scaling
Technical note
Nelson Felix and Luciana Meli
06 Nov 2020
4 minute read
IBM Research at SPIE 2020: New architectures and fabrications for AI hardware
Research
Nelson Felix
21 Feb 2020
4 minute read
- AI Hardware
- Semiconductors

Top collaborators

Luciana Meli

Senior Manager: Patterning & Metrology

Nicolas Loubet

STSM, Advanced Logic Technology Research

Mary Breton

Technical Assistant to Huiming Bu | Semiconductor Enablement Program Management & Infrastructure

Huimei Zhou

Senior Research Scientist-Master Inventor, Advanced Device Research