Monolithic Stacked FET with Stepped Channels for Future Logic Technologies
- Chen Zhang
- Seungmin Song
- et al.
- 2024
- IEDM 2024
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20 results for Dan J. Dechene
Backside power distribution for nanosheet technologies beyond 2nm
- Ruilong Xie
- Wonhyuk Hong
- et al.
- 2024
- VLSI Technology and Circuits 2024
Methodology Development to Benchmark Power Delivery Designs in Advanced Technology Nodes
- Nicholas A. Lanzillo
- A. Chu
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices
- H. Jagannathan
- B. Anderson
- et al.
- 2021
- IEDM 2021
Multiple-Vt Solutions in Nanosheet Technology for High Performance and Low Power Applications
- Ruqiang Bao
- Reinaldo A. Vega
- et al.
- 2019
- IEDM 2019
Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications
- J. Zhang
- S. Pancharatnam
- et al.
- 2019
- IEDM 2019
Next-Generation Logic Design Architecture for Vertical-Transport Nanosheets
- Biswanath (Biswa) Senapati
- Jeongho Do
- et al.
- 2023
- SPIE Advanced Lithography + Patterning 2023
DTCO Guided Process Integration: Case Studies From FEOL & BEOL with BSPDN
- Minhaz Abedin
- Shahrukh Khan
- et al.
- 2024
- ASMC 2024
DTCO Guided Process Integration: Case Studies from FEOL & BEOL with BSPDN Topic: DTCO/DFM
- Minhaz Abedin
- Shahrukh Khan
- et al.
- 2024
- ASMC 2024
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021