Methodology Development to Benchmark Power Delivery Designs in Advanced Technology Nodes

Abstract

Power delivery represents a key challenge in scaled technology nodes as interconnect wiring resistance increases and design constraints impact how much wiring can be used for power distribution. Here, we discuss several methodologies, including both pre-PDK and post-PDK, to benchmark the integrity of power delivery network designs with advanced technology features such as vertical FET (VTFET) transistor architecture, skip-level vias, buried power rails and backside power delivery. For a post-2nm node VTFET architecture, we employ a pre-PDK benchmarking to find that buried power rails can reduce gate delay by as much as 30%. For 5nm and 2nm technology nodes, we use existing PDKs to simulate backside power delivery networks (BS-PDN) and find that scaled logic area can be reduced by 10-30% while minimum-pitch interconnect RC delay can be reduced by as much as 70% depending on reference design.