Evaluation of (110) versus (001) Channel Orientation for Improved nFET/pFET Device Performance Trade-Off in Gate-All-Around Nanosheet Technology
- Shogo Mochizuki
- Nicolas Loubet
- et al.
- 2023
- IEDM 2023
Nicolas Loubet received the B.S. and M.S degrees in physics from Paul Sabatier University, Toulouse (Fr.), in 2000 and 2001. In 2003, he received a high-level Engineering degree in the field of Physics and Microelectronics from the National Institute of Applied Sciences (INSA) in Toulouse, and the PhD degree in the domain of Materials, Technology and Electronic Devices in 2006. From 2003 to 2008, he joined STMicroelectronics Research and Development group in front-end materials and epitaxy where he was engaged in the development of Advanced Epitaxy of Si and SiGe materials and developed the vapor-phase etching of SiGe for the fabrication of silicon-on-nothing (SON), Gate-All-Around and dielectric isolation transistors. In 2008, he joined the Silicon Technology Research Alliance at IBM Research in Albany, NY and the following years, his research focused on Junction and Strain module engineering for the 20nm, 14nm, 10nm, and 7nm CMOS device nodes using strained SOI and SGOI, SiGe relaxed buffer and ultra-low resistivity SiGe and SiC