Dureseti Chidambarrao

Title

STSM - Thermal & Design-Technology-Manufacturing Solutions

Bio

Dureseti (Chidu) Chidambarrao is a recognized expert in Modeling, semiconductor R&D, Design For Manufacturability, and Design Technology Co-Optimization. Chidu is currently a Senior Technical Staff Member at IBM Research where he leads cross-functional teams in Thermal Solutions for Chiplets and Advance Packaging and device architecture components of the 2nm program. Before joining IBM Research, Chidu worked at IBM Infrastructure where he led the Product-Technology-Interactions team to help deliver P/Z chips for IBM’s mainframes for the 14, 7, and 5nm technology nodes. He developed his deep process, device, and DTCO expertise while at the IBM Semiconductor R&D Center working on the 90nm through 22nm CMOS nodes. Chidu’s technical accomplishments have been recognized with multiple awards internally at IBM, including a Corporate Award in 2022, IBM’s highest technical recognition.

Chidu has over 225 US patents, is an IBM Master Inventor for 15 years, and has 65 publications. Chidu got his B Tech from the Indian Institute of Technology, Madras and his PhD from North Carolina State University.

Publications

Gate Resistance Test Structures Bounded by Local Layout Density to Characterize Metal Gate Height Variation in 7nm FinFET Technology
- - Justin Zhu
  - Katsunori Onishi
  - et al.
- 2024
- IEEE MDTS 2024
Cores, Cache, Content, and Characterization: IBM’s Second Generation 14-nm Product, z15
- - David Wolpert
  - Chris Berry
  - et al.
- 2020
- IEEE JSSC
IBM z15: Physical design improvements to significantly increase content in the same technology
- - Christopher Berry
  - David Wolpert
  - et al.
- 2020
- IBM J. Res. Dev
IBM z15: A 12-Core 5.2GHz Microprocessor
- - Christopher Berry
  - Brian Bell
  - et al.
- 2020
- ISSCC 2020
IBM z14: Processor characterization and power management for high-reliability mainframe systems
- - Christopher Berry
  - David Wolpert
  - et al.
- 2019
- IEEE JSSC
Identification and sensitivity analysis of a correlated ground rule system (design arc)
- - Eric Eastman
  - Dureseti Chidambarrao
  - et al.
- 2017
- SPIE Advanced Lithography 2017
High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Study of silicon strain in shallow trench isolation
- - M. Belyansky
  - N. Klymko
  - et al.
- 2010
- Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
Reduction of RTA-driven intra-die variation via model-based layout optimization
- - J.C. Scott
  - O. Gluschenkov
  - et al.
- 2009
- VLSI Technology 2009
(110) Channel, SiON gate-dielectric PMOS with record high I_on=1 mA/μm through channel stress and source drain external resistance (R _ext) engineering
- - B. Yang
  - A. Waite
  - et al.
- 2007
- IEDM 2007

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Patents

- 15 Apr 2024
- US
- 11960830
Exploratory Data Interface
- 18 Apr 2022
- US
- 11308257
Stacked Via Rivets In Chip Hotspots
- 11 Apr 2022
- US
- 11303285
Multi-mode Design And Operation For Transistor Mismatch Immunity
- 16 Nov 2020
- US
- 10839133
Circuit Layout Similarity Metric For Semiconductor Testsite Coverage
- 20 Apr 2020
- US
- 10628544
Optimizing Integrated Circuit Designs Based On Interactions Between Multiple Integration Design Rules
- 06 Apr 2020
- US
- 10614190
Deep Trench Floorplan Distribution Design Methodology For Semiconductor Manufacturing
- 16 Mar 2020
- US
- 10592627
Optimizing Integrated Circuit Designs Based On Interactions Between Multiple Integration Design Rules
- 20 Mar 2019
- DE
- 112012000310.1
Silicon Nanotube Mosfet
- 15 Jun 2017
- CN
- ZL201280010634.4
Silicon Nanotube Mosfet
- 08 May 2017
- US
- 9646124
Modeling Transistor Performance Considering Non-uniform Local Layout Effects

Top collaborators

Dureseti Chidambarrao

Title

Bio

Publications

Gate Resistance Test Structures Bounded by Local Layout Density to Characterize Metal Gate Height Variation in 7nm FinFET Technology

Cores, Cache, Content, and Characterization: IBM’s Second Generation 14-nm Product, z15

IBM z15: Physical design improvements to significantly increase content in the same technology

IBM z15: A 12-Core 5.2GHz Microprocessor

IBM z14: Processor characterization and power management for high-reliability mainframe systems

Identification and sensitivity analysis of a correlated ground rule system (design arc)

High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization

Study of silicon strain in shallow trench isolation

Reduction of RTA-driven intra-die variation via model-based layout optimization

(110) Channel, SiON gate-dielectric PMOS with record high I_on=1 mA/μm through channel stress and source drain external resistance (R _ext) engineering

Patents

Exploratory Data Interface

Stacked Via Rivets In Chip Hotspots

Multi-mode Design And Operation For Transistor Mismatch Immunity

Circuit Layout Similarity Metric For Semiconductor Testsite Coverage

Optimizing Integrated Circuit Designs Based On Interactions Between Multiple Integration Design Rules

Deep Trench Floorplan Distribution Design Methodology For Semiconductor Manufacturing

Optimizing Integrated Circuit Designs Based On Interactions Between Multiple Integration Design Rules

Silicon Nanotube Mosfet

Silicon Nanotube Mosfet

Modeling Transistor Performance Considering Non-uniform Local Layout Effects

Top collaborators

Ramon Bertran Monfort

Alper Buyuktosunoglu

Hasan M Nayfeh

Vijay Narayanan