Allen Gabor

Title

Distinguished Engineer

Bio

Allen Gabor is a Senior Technical Staff Member at IBM. He has worked in the field of lithography at Arch Chemicals, GlobalFoundries and IBM. This work has included photoresist development, CD control, overlay minimization and 193 dry, immersion and EUV insertion. He received his PhD (1996) in Materials Science and Engineering from Cornell University based on his work on block copolymer photoresists. He is the author of more than 50 journal papers and holder of over 30 patents. He currently serves on the program committee for SPIE Extreme Ultraviolet (EUV) Lithography Conference and is a senior member of SPIE.

Publications

Impact of high-NA half-field to full-field overlay performance by Monte Carlo simulations
- - Romain Lallement
  - Daniel Schmidt
  - et al.
- 2023
- OEN 2023
Bayesian dropout approximation in deep learning neural networks: Analysis of self-Aligned quadruple patterning
- - Scott D. Halle
  - Derren N. Dunn
  - et al.
- 2022
- JM3
Predicting overlay mark performance based on process emulation and optical simulation
- - Sagarika Mukesh
  - Jack Wong
  - et al.
- 2022
- SPIE Advanced Lithography 2022
Effect of high NA "half-field" printing on overlay error
- - Allen Gabor
  - Martin Burkhardt
  - et al.
- 2021
- SPIE Advanced Lithography 2021
EUV single exposure via patterning at aggressive pitch
- - Jing Guo
  - Jennifer Church
  - et al.
- 2021
- SPIE Advanced Lithography 2021
Bayesian dropout approximation in deep learning neural networks: Analysis of self-aligned quadruple patterning
- - Scott D. Halle
  - Max O. Bloomfield
  - et al.
- 2020
- SPIE Advanced Lithography 2020
Characterization of EUV image fading induced by overlay corrections using pattern shift response metrology
- - Daniel Schmidt
  - Roger Cornell
  - et al.
- 2019
- EUVL 2019
Overlay error statistics for multiple-exposure patterning
- - Allen Gabor
  - Nelson Felix
- 2019
- J. Micro/Nanolithogr. MEMS MOEMS
Overlay statistics for multiple exposure patterning
- - Allen H. Gabor
  - Nelson M. Felix
- 2017
- SPIE Advanced Lithography 2017
Mix-and-match considerations for EUV insertion in N7 HVM
- - Xuemei Chen
  - Allen Gabor
  - et al.
- 2017
- SPIE Advanced Lithography 2017

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Patents

- 31 Jan 2022
- US
- 11239077
Litho-etch-litho-etch With Self-aligned Blocks
- 25 Mar 2019
- US
- 10242952
Registration Mark Formation During Sidewall Image Transfer Process
- 06 Aug 2018
- US
- 10043760
Registration Mark Formation During Sidewall Image Transfer Process
- 01 Jan 2018
- US
- 9859224
Registration Mark Formation During Sidewall Image Transfer Process
- 17 Oct 2016
- US
- 9472506
Registration Mark Formation During Sidewall Image Transfer Process
- 02 Jun 2015
- US
- 9046788
Method For Monitoring Focus On An Integrated Wafer
- 30 Sep 2014
- US
- 8847416
Multi-layer Chip Overlay Target And Measurement
- 18 Mar 2014
- US
- 8673165
Sidewall Image Transfer Process With Multiple Critical Dimensions
- 17 Dec 2013
- US
- 8609322
Process Of Making A Lithographic Structure Using Antireflective Materials
- 26 Nov 2013
- US
- 8592110
Alignment Marks For Multi-exposure Lithography

Top collaborators

Allen Gabor

Title

Bio

Publications

Impact of high-NA half-field to full-field overlay performance by Monte Carlo simulations

Bayesian dropout approximation in deep learning neural networks: Analysis of self-Aligned quadruple patterning

Predicting overlay mark performance based on process emulation and optical simulation

Effect of high NA "half-field" printing on overlay error

EUV single exposure via patterning at aggressive pitch

Bayesian dropout approximation in deep learning neural networks: Analysis of self-aligned quadruple patterning

Characterization of EUV image fading induced by overlay corrections using pattern shift response metrology

Overlay error statistics for multiple-exposure patterning

Overlay statistics for multiple exposure patterning

Mix-and-match considerations for EUV insertion in N7 HVM

Patents

Litho-etch-litho-etch With Self-aligned Blocks

Registration Mark Formation During Sidewall Image Transfer Process

Registration Mark Formation During Sidewall Image Transfer Process

Registration Mark Formation During Sidewall Image Transfer Process

Registration Mark Formation During Sidewall Image Transfer Process

Method For Monitoring Focus On An Integrated Wafer

Multi-layer Chip Overlay Target And Measurement

Sidewall Image Transfer Process With Multiple Critical Dimensions

Process Of Making A Lithographic Structure Using Antireflective Materials

Alignment Marks For Multi-exposure Lithography

Top collaborators

Nelson Felix

Luciana Meli

Mary Breton