IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area and Reliability

Abstract

IBM Telum II is an 8 core 5.5 GHz microprocessor for the zNext system. Key capacity and performance improvements are achieved through enhancements to the core, AI accelerator, and the use of high-density SRAM cell to increase cache size. A new on-chip data processing unit is included with an initial use of IO acceleration. Telum II maintains high reliability and a power profile within 5% of the prior generation while simultaneously increasing frequency and increasing latch count by 40%.