Cores, Cache, Content, and Characterization: IBM’s Second Generation 14-nm Product, z15

Abstract

The IBM z15 system improves upon the prior-generation z14 design within the same chip footprint and technology node, while featuring the addition of two cores, 33%/100%/43% additional L2/L3/L4 cache, as well as additional core features and on-chip accelerators. The largest 5-drawer system configuration includes 20 central processor (CP) chips, five system controller (SC) chips, and 40 TB of memory. With ~200 cores across all CP chips operating with 99.99999% uptime at 5.2 GHz, z15 achieves a 25% increase in system capacity and a 14% single thread performance improvement over the z14 system. In this article, we describe the key design factors and system/characterization refinement that enabled these results, including the novel 2-Mb embedded dynamic random access memory (eDRAM) cell, a new voltage droop monitor, a more comprehensive power reduction infrastructure to reduce power-limited yield, results on reliability-limited versus power-limited yield, and a characterization effort for exploring even higher frequencies, with our first reported 6-GHz values achieved in the lab at customer temperatures and voltages.