Leakage aware Si/SiGe CMOS FinFET for low power applications
G. Tsutsui, C. Durfee, et al.
VLSI Technology 2018
We report that n-dipole and p-dipole (dual dipoles) can be co-integrated to provide a more flexible volumeless multiple threshold voltage(multi-Vt) solution in FinFET and Nanosheet (NS) technologies. The p-dipole process for dual dipoles co-integration is identified. When the Vt shift is less than 100m V, the mobility is slightly degraded, but other properties are not clearly affected. The improved pFET performance is from the Vt reduction. The dipole co-integration also provides a novel method for Vt definition via dipole Vt compensation. Our selective dipole enablement can implement near bandedge (BE) multi- Vt for high performance application.
G. Tsutsui, C. Durfee, et al.
VLSI Technology 2018
Hazar Yueksel, Ramon Bertran, et al.
MLSys 2020
Laura Bégon-Lours, Mattia Halter, et al.
MRS Spring Meeting 2023
Lin Dong, Steven Hung, et al.
VLSI Technology 2021