Victor Chan

Overview

Victor Chan

Title

Yield learning & Diag Eng Prof

Location

IBM Research - Albany Albany, NY USA

Bio

Current / Recent: STSM in Yield / characterization of 2nm Nanosheet Logic; Analog AI hardware and chiplet technologies.
Working in semiconductor industry over 20 years in IBM.
Technical leadership in FEOL integration and device teams of CMOS 90 to deep sub-micron in bulk / SOI technologies, innovative and inventive delivery of process technologies from concept to qualification to manufacturing.
Specialties include semiconductor device & integration in R&D and production, product - customer deployment, technology licensing and technical support. Extensive experience in running lots and characterization of device / inline-metrology / PLY / Health-of-line and yield data. Device, SRAM and product yield learning and improvement through Hands-on data analysis.

Publications

Interaction of middle-of-line (MOL) temperature and mechanical stress on 90nm hi-speed device performance and reliability
- - K.Y. Lim
  - V. Chan
  - et al.
- 2005
- ESSDERC 2005
Dual stress liner enhancement in hybrid orientation technology
- - C. Sheraw
  - M. Yang
  - et al.
- 2005
- VLSI Technology 2005
On the scalability and carrier transport of advanced CMOS devices
- - Meikei Ieong
  - Leland Chang
  - et al.
- 2005
- ICICDT 2005
Strain for CMOS performance improvement
- - Victor Chan
  - Ken Rim
  - et al.
- 2005
- CICC 2005
High performance and low power transistors integrated in 65nm bulk CMOS technology
- - Z. Luo
  - A. Steegen
  - et al.
- 2004
- IEDM 2004
On the integration of CMOS with hybrid crystal orientations
- - M. Yang
  - V. Chan
  - et al.
- 2004
- VLSI Technology 2004
High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations
- - M. Yang
  - M. Ieong
  - et al.
- 2003
- IEDM 2003
Three dimensional CMOS devices and integrated circuits
- - Meikei Ieong
  - Kathryn W. Guarini
  - et al.
- 2003
- CICC 2003

Visit Google Scholar

Patents

- 20 Mar 2007
- US
- 7193254
Structure And Method Of Applying Stresses To Pfet And Nfet Transistor Channels For Improved Performance
- 09 Jan 2007
- US
- 7161169
Enhancement Of Electron And Hole Mobilities In <110> Si Under Biaxial Compressive Strain
- 12 Dec 2006
- US
- 7148559
Substrate Engineering For Optimum Cmos Device Performance
- 20 Feb 2006
- US
- 7001844
Material For Contact Etch Layer To Enhance Device Performance
- 13 Dec 2005
- US
- 6975133
Logic Circuits Having Linear And Cellular Gate Transistors
- 06 Sep 2005
- US
- 6939814
Increasing Carrier Mobility In Nfet And Pfet Transistors On A Common Wafer
- 23 Nov 2004
- US
- 6821826
Three Dimensional Cmos Integrated Circuits Having Device Layers Built On Different Crystal Orient Wafers

Top collaborators

IA

Ishtiaq Ahsan

Ishtiaq Ahsan

Senior Manager, Yield/ Test & Characterization, IBM Semiconductor Technology Research & Development

VN

Vijay Narayanan

Vijay Narayanan

IBM Fellow & Strategist, Physics of AI. Senior Manager, PCM and AI Materials

GB

Geoffrey Burr

Geoffrey Burr

Distinguished RSM