Design of Analog-AI Hardware Accelerators for Transformer-based Language Models (Invited)
- Geoffrey Burr
- Sidney Tsai
- et al.
- 2023
- IEDM 2023
IBM 5 yrs 8 mos5 yrs 8 mos Senior Manager, Yield/Characterization, 2nm Logic, AI Hardware & Chiplet Technologies Senior Manager, Yield/Characterization, 2nm Logic, AI Hardware & Chiplet Technologies
Jul 2021 - Present · 2 yrs 11 mosJul 2021 to Present · 2 yrs 11 mos Albany, New York, United States ·Albany, New York, United States · On-site Senior Manager, AI Prodect Yield/Characterization, IBM AI Hardware Center, Albany Senior Manager, AI Prodect Yield/Characterization, IBM AI Hardware Center, Albany
Jul 2019 - Jun 2021 · 2 yrsJul 2019 to Jun 2021 · 2 yrs Albany, New York AreaAlbany, New York Area
Project Lead, AI Product Yield/CharacterizationProject Lead, AI Product Yield/Characterization Oct 2018 - Jul 2019 · 10 mosOct 2018 to Jul 2019 · 10 mos Artificial intelligence center, IBM Research, Albany,NYArtificial intelligence center, IBM Research, Albany,NY
GlobalFoundries Senior Manager/ Deputy Director, Advance Technology Development, YieldSenior Manager/ Deputy Director, Advance Technology Development, Yield GLOBALFOUNDRIESGLOBALFOUNDRIES Jul 2015 - Sep 2018 · 3 yrs 3 mosJul 2015 to Sep 2018 · 3 yrs 3 mos Malta, NYMalta, NY Manager, 7nm SRAM/Logic yield teamManager, 7nm SRAM/Logic yield team
IBM 14 yrs14 yrs Hopewell Junction, NYHopewell Junction, NY Senior Engineering Manager, Yield/Characterization,FinFET/Planer Semiconductor Technology DevelpmntSenior Engineering Manager, Yield/Characterization,FinFET/Planer Semiconductor Technology Develpmnt Aug 2011 - Jul 2015 · 4 yrsAug 2011 to Jul 2015 · 4 yrs • End to end characterization yield project planning which includes owning IC test structure design strategy, testing and data analysis plan, and overall functional yield (SRAM, Digital Logic) characterization plan. • Responsible for driving yield improvement together with broad cross functional circuit design/process/integration/lithography/device team. • Responsible for client facing communication on yield and performance • Responsible for managing the memory and logic yield data analysis and test group (people manager).• End to end characterization yield project planning which includes owning IC test structure design strategy, testing and data analysis plan, and overall functional yield (SRAM, Digital Logic) characterization plan. • Responsible for driving yield improvement together with broad cross functional circuit design/process/integration/lithography/device team. • Responsible for client facing communication on yield and performance • Responsible for managing the memory and logic yield data analysis and test group (people manager). Technology yield characterization program manager (lead yield engineer), 45nm/22nm, IBMTechnology yield characterization program manager (lead yield engineer), 45nm/22nm, IBM
Aug 2005 - Aug 2011 · 6 yrs 1 moAug 2005 to Aug 2011 · 6 yrs 1 mo • Responsible for yield characterization program management for state-of-the art semiconductor technologies from early development to full manufacturing qualification. • Responsible for driving yield improvement together with broad cross functional circuit design/process/integration/lithography/device team. • Responsible for managing and maintaining the technology yield problem list and driving actions to fix the top issues. • Responsible for identifying root cause of fail of yield issues, quantifying yield impact for various fail modes and for predicting yield improvement on future hardware. • Responsible for owning yield step-up plan from early development to full manufacturing.• Responsible for yield characterization program management for state-of-the art semiconductor technologies from early development to full manufacturing qualification. • Responsible for driving yield improvement together with broad cross functional circuit design/process/integration/lithography/device team. • Responsible for managing and maintaining the technology yield problem list and driving actions to fix the top issues. • Responsible for identifying root cause of fail of yield issues, quantifying yield impact for various fail modes and for predicting yield improvement on future hardware. • Responsible for owning yield step-up plan from early development to full manufacturing. MOSFET Device Characterization EngineerMOSFET Device Characterization Engineer
Aug 2001 - Aug 2006 · 5 yrs 1 moAug 2001 to Aug 2006 · 5 yrs 1 mo Joined IBM as a MOSFET device characterization engineer with an electrical engineering degree with solid state electronics background. Was responsible for volume data analysis of MOSFET device parameters (Ion, Ioff etc) of state of the art semiconductor technologies in both development and manufacturing. • Responsible for semiconductor MOSFET device characterization in development and manufacturing. • Technology power performance analysis based on ring oscillator and leakage data. • Represented IBM as device physics expert to external customers. • Cp-Cpk analysis of device parameters for technology qualification and tracking.