2nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
- C. Ortolland
- Daniel Jaeger
- et al.
- 2013
- IEDM 2013
Publications
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194 results for Vijay Narayanan
New layout dependency in high-k/metal gate MOSFETs
- M. Hamaguchi
- Deleep R. Nair
- et al.
- 2011
- IEDM 2011
Fundamental aspects of HfO 2-based high-k metal gate stack reliability and implications on t inv-scaling
- E. Cartier
- Andreas Kerber
- et al.
- 2011
- IEDM 2011
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- S. Krishnan
- U. Kwon
- et al.
- 2011
- IEDM 2011
Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t-tuning dipoles with gate-first process
- T. Ando
- M.M. Frank
- et al.
- 2009
- IEDM 2009
Trigate 6T SRAM scaling to 0.06 μm2
- M. Guillorn
- J. Chang
- et al.
- 2009
- IEDM 2009
Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate
- K. Henson
- H. Bu
- et al.
- 2008
- IEDM 2008
Extendibility of NiPt silicide contacts for CMOS technology demonstrated to the 22-nm node
- Kazuya Ohuchi
- Christian Lavoie
- et al.
- 2007
- IEDM 2007
Fundamental understanding and optimization of PBTI in nFETs with SiO 2/HfO2 gate stack
- E. Cartier
- B.P. Linder
- et al.
- 2006
- IEDM 2006
Systematic study of workfunction engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks
- Y.-H. Kim
- C. Cabral Jr.
- et al.
- 2005
- IEDM 2005