Asynchronous interlocked pipelined CMOS circuits operating at 3.3-4.5Ghz

Abstract

Interlocked pipelined complementary metal oxide semiconductor (IPCMOS) to analyze microprocessor chip performance, power, noise and clock synchronization was discussed. The asynchronous handshaking local clock circuits in IPCMOS were loaded with 40 latches to simulate practical loading. A high-speed interlocking was achieved by IPCMOS using the combination of a static NOR and the input switch.