DRAM variable retention time
P. Restle, J.W. Park, et al.
IEDM 1992
On-chip interconnect delays are becoming an increasingly important factor for high-performance microprocessors. Consequently, critical on-chip wiring must be carefully optimized to reduce and control interconnect delays, and accurate interconnect modeling has become more important. This paper shows the importance of including transmission line effects in interconnect modeling of the on-chip clock distribution of a 400 MHz CMOS microprocessor. Measurements of clock waveforms on the microprocessor showing 30 ps skew were made using an electron beam prober. Waveforms from a test chip are also shown to demonstrate the importance of transmission line effects.
P. Restle, J.W. Park, et al.
IEDM 1992
A. Deutsch, M. Scheuermann, et al.
IEEE Microwave and Guided Wave Letters
J.N. Burghartz, M. Soyuer, et al.
IEDM 1995
J.N. Burghartz, M. Soyuer, et al.
ESSDERC 1995