SiGe BICMOS 3.3V clock and data recovery circuits for 10Gb/s serial transmission systems

Abstract

A 12.5 Gb/s and a 9.95 Gb/s fully monolithic SiGe BiCMOS 3.3V clock and data recovery (CDR) circuits were described. They were developed for SONET OC-192 and 10GBE applications. Two different loops, one for frequency acquisition and other for data recovery were used. The small pull-in range of a PLL in data recovery caused the requirement of frequency-acquistion. A delay interpolating ring oscillator was used in each circuit.