A 14-ns 4-Mb CMOS DRAM with 300-mW Active Power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18 × 6.38-mm² chip, organized as either 512K word × 8 b or 1M word × 4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V Vand provision of address multiplexing. The high level of performance is achieved by using a shortsignal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V Vto a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and a boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time. © 1992 IEEE