Embedded dynamic random access memory

Abstract

For several decades, the 1-transistor Dynamic Random Access Memory (DRAM) has been the dominant choice for high density and low cost semiconductor memory in computing systems. Recently, advancements in miniaturization have allowed integration of DRAM on the same die with the processor. Key advancements in memory technology, architecture and circuit design required to capitalize on the merger of DRAM and logic are described here. After reviewing the history and accomplishments in embedded DRAM over the past decade, details of three generations of embedded DRAM development at IBM are discussed. In the third generation, which is the 130nm technology, three specialized DRAM macros have been developed. The first is a general purpose growable design targeted specifically for the ASIC's environment. The second is an area optimized design which includes special features for reducing standby and data retention current. The third macro employs a novel destructive read architecture with a single-ended direct sensing scheme for enabling random cycle time as fast as 3.3ns for network applications.