A 0.88pJ/bit 112Gb/s PAM4 Transmitter with 1V_ppd Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS

Abstract

A 0.88pJ/bit 112Gb/s PAM4 transmitter is reported in 7nm FinFET CMOS with 1V ppd output amplitude. The quarter-rate TX architecture implements a 5-tap analog FFE using tap extension circuitry, which permits higher FFE tap count than conventional quarter-rate architectures without requiring complex clocking. A key feature of the FFE construction is the use of fully re-assignable CML driver segments among FFE taps, which allows a reduced number of segments for lower capacitance and higher driver bandwidth.