Matthias Brändli

Publications

• A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC

  • • Jaewon Lee
    • Seoyoung Jang
    • et al.
  • 2024
  • IEEE TCAS-II

• A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-based Wireline Transceivers

  • • Donggeon Kim
    • Yujin Choi
    • et al.
  • 2024
  • IEEE TCAS-I

• A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links

  • • Jaewon Lee
    • Seoyoung Jang
    • et al.
  • 2024
  • ISCAS 2024

• A 0.88pJ/bit 112Gb/s PAM4 Transmitter with 1V<sub>ppd</sub output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS

  • • Zeynep Toprak Deniz
    • Tod Dickson
    • et al.
  • 2024
  • VLSI Technology and Circuits 2024

• A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation On RFSoC Platform

  • • Jaewon Lee
    • Seoyoung Jang
    • et al.
  • 2024
  • IEEE TCAS-II

• Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration

  • • Tod Dickson
    • Zeynep Toprak Deniz
    • et al.
  • 2024
  • CICC 2024

• A DAC/ADC-based Wireline Transceiver Datapath Functional Verification on RFSoC Platform

  • • Jaewon Lee
    • Seoyoung Jang
    • et al.
  • 2024
  • IEEE TCAS-II

• Design of synchronous frequency dividers in 5-nm FinFET CMOS technology

  • • Marcel Kossel
    • Pier Andrea Francese
    • et al.
  • 2023
  • Electronics Letters

• Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology

  • • Sandro Widmer
    • Marcel Kossel
    • et al.
  • 2023
  • IEEE TCAS-II

• A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

  • • Manuel Le Gallo
    • Riduan Khaddam-Aljameh
    • et al.
  • 2023
  • Nature Electronics