F3: Serving Files Efficiently in Serverless Computing
Alex Merenstein, Vasily Tarasov, et al.
SYSTOR 2023
This brief presents a discrete multi-tone (DMT) wireline transceiver (TRX) datapath and introduces the RFSoC-based real-time hardware platform to quickly sweep the optimum bit and power loading profile constrained by the peak-to-average-power ratio (PAPR). The datapath is implemented based on 32-parallel multi-path delay feedback (MDF) fast Fourier transform (FFT)/inverse FFT (IFFT) processors to save resources, integrating with the sign-sign least mean square (SS-LMS) engine. The loading is computed for the channel signal-to-noise ratio (SNR) and PAPR. The platform consists of 2.048 GS/s data converters, the DMT datapath implemented on programmable logic (PL) running at 64 MHz, and the channel board. This system enables a quick bit-error-rate (BER) test at an order of 1.0E-9, accelerating the finding of optimal loading with realistic hardware effects and random clipping events. Experimental results show that the data rate could reach a maximum of 6.82 Gb/s at a BER of 5.7E-4 and a minimum BER of 3.7E-7 for a target data rate of 4.81 Gb/s with a channel exhibiting 16.3 dB insertion loss (IL) at Nyquist.
Alex Merenstein, Vasily Tarasov, et al.
SYSTOR 2023
Xiaoxiong Gu, Duixian Liu, et al.
ECTC 2021
Alper Buyuktosunoglu, David Trilla Rodriguez, et al.
HPCA 2024
Mengmei Ye, Angelo Ruocco
KVM Forum 2022