A timing analysis algorithm for circuits with levelsensitive latches
- Jin Fuw Lee
- Donald T. Tang
- et al.
- 1996
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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23 results for D.T. Tang
Timing analysis algorithm for circuits with level-sensitive latches
- Jin-Fuw Lee
- D.T. Tang
- et al.
- 1996
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Algorithm for incremental timing analysis
- Jin-Fuw Lee
- D.T. Tang
- 1995
- DAC 1995
Timing analysis algorithm for circuits with level-sensitive latches
- Jin-Fuw Lee
- D.T. Tang
- et al.
- 1994
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HIMALAYAS - a hierarchical compaction system with a minimized constraint set
- Jin-Fuw Lee
- D.T. Tang
- 1992
- ICCAD 1992
VLSI Layout Compaction with Grid and Mixed Constraints
- Jin-Fuw Lee
- Donald T. Tang
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Hierarchical Global Wiring Algorithm for Custom Chip Design
- W.K. Luk
- Paolo Sipala
- et al.
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ON VLSI LAYOUT COMPACTION WITH MIXED GRID AND EDGE CONSTRAINTS.
- Jin-Fuw Lee
- D.T. Tang
- 1985
- ICCD 1985
Hierarchical global wiring for custom chip design
- W.K. Luk
- D.T. Tang
- et al.
- 1986
- DAC 1986
Logic Test Pattern Generation Using Linear Codes
- Donald T. Tang
- Chin-Long Chen
- 1984
- IEEE TC