D.T. Lee, Hsu Chang, et al.
IEEE TC
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the modified shortest and longest path method. The computational complexity of our algorithm is generally better than that of known algorithms in the literature. The implementation (CYCLOPSS) has been applied to an industrial chip to verify the clock schedules.
D.T. Lee, Hsu Chang, et al.
IEEE TC
Jin-Fuw Lee, D.T. Tang
DAC 1995
W.K. Luk, D.T. Tang, et al.
DAC 1986
C.K. Wong, Don Coppersmith
Journal of the ACM