Extendable and Manufacturable Volume-less Multi-Vt Solution for 7nm Technology Node and beyond
- Ruqiang Bao
- Huimei Zhou
- et al.
- 2018
- IEDM 2018
Publications
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194 results for Vijay Narayanan
High Performance InGaAs Gate-All-Around Nanosheet FET on Si Using Template Assisted Selective Epitaxy
- S. Lee
- Cheng-Wei Cheng
- et al.
- 2018
- IEDM 2018
High performance and reliable strained SiGe PMOS FinFETs enabled by advanced gate stack engineering
- Pouya Hashemi
- Takashi Ando
- et al.
- 2017
- IEDM 2017
A comparative study of strain and Ge content in Si1-xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs
- Choonghyun Lee
- Shogo Mochizuki
- et al.
- 2017
- IEDM 2017
CMOS compatible MIM decoupling capacitor with reliable sub-nm EOT high-k stacks for the 7 nm node and beyond
- Takashi Ando
- Eduard Cartier
- et al.
- 2016
- IEDM 2016
Technology viable DC performance elements for Si/SiGe channel CMOS FinFTT
- G. Tsutsui
- Ruqiang Bao
- et al.
- 2016
- IEDM 2016
High performance 14nm SOI FinFET CMOS technology with 0.0174μm2 embedded DRAM and 15 levels of Cu metallization
- C.-H.C-H. Lin
- Brian Greene
- et al.
- 2014
- IEDM 2014
High-performance CMOS-compatible self-aligned In0.53Ga0.47As MOSFETs with GMSAT over 2200 μs/μm at VDD = 0.5 v
- Yanning Sun
- Amlan Majumdar
- et al.
- 2014
- IEDM 2014
Replacement metal gate resistance in FinFET architecture modelling, validation and extendibility
- Ruqiang Bao
- Brian Greene
- et al.
- 2015
- IEDM 2015
Understanding and mitigating High-k induced device width and length dependencies for FinFET replacement metal gate technology
- Takashi Ando
- Tenko Yamashita
- et al.
- 2015
- IEDM 2015