The circuits and physical design of the synergistic processor element of a CELL processor

Abstract

A 32b 4-way SIMD dual-issue Synergistic Processor Element of a CELL Processor is developed with 20.9 million transistors in 14.8mm 2 using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the non-SRAM area. ISA, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56°C.