Design methodology for a 1.0 GHz microprocessor
S.D. Posluszny, Naoaki Aoki, et al.
ICCD 1998
This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.
S.D. Posluszny, Naoaki Aoki, et al.
ICCD 1998
H.P. Hofstee, Naoaki Aoki, et al.
ISSCC 2000
D.C. Pham, E. Behnen, et al.
CICC 2005
S.D. Posluszny, Naoaki Aoki, et al.
DAC 2000