1GHz fully pipelined 3.7ns Address access time 8kx1024 embedded DRAM macro

Abstract

Embedded dynamic random access memory (DRAM) macro of 1GHz fully pipelined 3.7ns address access time 8K×1024 was presented. This macro was based on a logic-based DRAM technology and designed as a DRAM cache for a future gigahertz microprocesser. The macro received four external signals namely: 3 commands, 1 clock, and a 13b address signals. Fabrication of the macro was done in CMOS8S embedded DRAM technology.