D. Heidel, S. Dhong, et al.
VTS 1998
A 64b 1 GHz single-issue PowerPC processor containing 19M transistors was studied. The microprocessor was fabricated on a 0.12 μm six-layer copper interconnect complementary metal oxide semiconductor (CMOS). The processor was implemented using delayed-reset and self-resetting dynamic circuit macros. The new features in the chip included fully pipelined floating-point unit (FPU), sum-addressed memory management units (MMU), improved clock generation and distribution and microarchitecture and floorplan to balance critical paths.
D. Heidel, S. Dhong, et al.
VTS 1998
R. Scheuerlein, W.J. Gallagher, et al.
ISSCC 2000
S.D. Posluszny, Naoaki Aoki, et al.
DAC 2000
S.E. Schuster, W. Reohr, et al.
ISSCC 2000