Templated epitaxial growth and synthesis of III-V nanostructures on silicon

1D semiconducting nanowires (NWs) have gained great attention as they are one of the best-defined classes of nanoscale building blocks for bottom-up assembly of next generation electronic, sensing, and optoelectronic devices, whether in the form of individual NWs [1] or their arrays [2]. While the growth based on physical epitaxy results in the high-quality NWs, due to the challenging harvesting and aligning to the existing features on a chip, their integration with the silicon-based platform is cost and time consuming. In order to utilize the advantages of semiconducting nanowires on silicon, an integration method called template-assisted selective epitaxy (TASE) was developed, which combines selective epitaxy and growth direction control. This technology in combination with a metal-organic chemical vapor deposition (MOCVD) was successfully applied for monolithic integration of for example InAs and GaAsSb on silicon or silicon-on-insulator (SOI) substrates resulting in a wide range of electronic devices [3, 4].

In this work we will explore the possibilities of III-V nanowires integration on Si platforms, including alternative synthesis routes for materials which are challenging to grow with physical epitaxy methods [5].

Acknowledgements The research was carried out thanks to the financial support of the Marie Skłodowska-Curie Action H2020 EU TECNO (894326).

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