Silicon Germanium heterojunction bipolar transistor ESD power clamps and the Johnson Limit

Abstract

Achieving radio frequency (RF) performance circuit objectives and electrostatic discharge (ESD) protection will continue to challenge future technology. In this study, we use the ultimate limitation of the transistor (e.g., known as the Johnson Limit) as a means to provide an ESD power clamp by providing a first low breakdown trigger device and a second high breakdown clamp device. Using the inverse relationship between unity current gain cutoff frequency and breakdown voltage, ESD power clamps are constructed using epitaxial base pseudomorphic Silicon Germanium heterojunction transistors in a common-collector Darlington configuration. ESD experimental test results from human body model (HBM), machine model (MM) and transmission line pulse (TLP) testing demonstrate the scaling of ESD power clamps. Design studies of alternative implementations, resistor ballasting and alternative triggers will be discussed. As a comparative analysis, the SiGe-based ESD power clamps will be compared to CMOS MOSFET-based ESD power clamps. A new dimensionless group is defined to quantify the relationship between the power-to-failure and the maximum Johnson limit power.