On the retention time distribution of dual-channel vertical DRAM technologies

Abstract

In this paper, we discuss unique opportunities in vertical transistor DRAM technology for retention time optimization. By fully utilizing the asymmetric vertical device design, we demonstrate that shallow Arsenic bitline junction, reduced buried strap outdiffusion, and locally lowered p-well concentration can be incorporated in vertical DRAM transistors to pave the scaling path without degrading retention time. A methodology to probe storage node side leakage current by the use of gated-diode measurements is established. Various mechanisms that impact retention time distribution are discussed. Furthermore, we demonstrate that the degradation of tail retention time due to high junction electric field can be minimized by aggressively lowering the junction depletion volume and defect levels.