Ingrid Shao, Lubomyr T. Romankiw, et al.
Journal of Crystal Growth
This paper reports a novel, non-epitaxial raised source/drain approach to decrease the parasitic series resistance in nMOSFETs fabricated on UTSOI using a selective electroless metal deposition process. A metallic layer selectively deposited in the source/drain and gate nickel or cobalt suicide regions significantly reduces the parasitic external resistance in nMOSFETs with 10nm body thickness and gate lengths down to 20nm. This approach is fully compatible with a conventional CMOS process flow for both Co and Ni suicides and eliminates the added complexity of a conventional raised source/drain approach.. The extremely high deposition selectivity of the process is confirmed through gate leakage measurements. © 2006 IEEE.
Ingrid Shao, Lubomyr T. Romankiw, et al.
Journal of Crystal Growth
J. Yuan, S.S. Tan, et al.
VLSI Technology 2006
H. Shang, L. Chang, et al.
VLSI Technology 2006
R.S. Shenoy, K. Gopalakrishnan, et al.
VLSI Technology 2006