A 45nm low cost low power platform by using integrated dual-stress-liner technology

Abstract

Device performance has been boosted by integrating dual-stress-liners (DSL) in a 45nm low power platform as a cost effective approach. A stress-proximity-technique (SPT) has been explored to improve device performance without adding process complexity. Record drain currents of 840/490 uA/um have been achieved for NMOS and PMOS, respectively, at 1.2V and off-leakage current of 1nA/um. Junction profiles have been optimized to reduce the gateinduced-drain-leakage (GIDL). An asymmetric IO has been integrated into this low power technology for the first time, offering multiple advantages including low cost, performance gain up to 30% and reliability improvement as well. © 2006 IEEE.