Guided Random Synthetic Layout Generation and Machine-Learning Based Defect Prediction for Leading Edge Technology Node Development

Abstract

In this paper we propose a flow to combine synthetic layout generation (LSG) and machine-learning based defect prediction (SONR) to accelerate new technology node development for logic devices. We start with limited ground rules for critical logic design, and create random guided synthetic layout (LSG patterns). These patterns can complement existing functional and OPCV macros. Testchip SEM inspection on LSG patterns can identify multiple types of process hotspots in a concentrated region, improving the defect inspection efficiency. The silicon results can be used to calibrate Calibre SONR defect models. Hotspot analysis based on process and design related features can accelerate identification of the root cause. These hotspots can lead to refinement of litho, etch and CMP processes and/or update of a specific design rule, therefore, accelerating process node development and yield ramp. The predicted process pinch points in functional design area through SONR will be compared with traditional inspection methods.