Exploiting combinatorial redundancy for offset calibration in flash ADCs

Abstract

Process variations in advanced CMOS nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge for circuits such as comparators. In this paper we describe and demonstrate the details of a statistical element selection (SES) methodology that relies on the combinatorial growth of subsets of selectable circuit elements (e.g., input transistors in a comparator) to provide redundancy for post-manufacturing calibration of specifications (e.g., offset). A test chip consisting of an array of digitally calibrated comparators with built-in combinatorial redundancy was manufactured in 65 nm bulk CMOS. Over 99.5% of the comparators satisfy the given offset specification compared to 15% for Pelgrom-type sizing. A second test chip in the same process consists of an 8-bit, 1.5 GS/s flash ADC and achieves 37 db SNDR at low frequencies. The total power is 35 mW, 20 mW in the S&H and 15 mW in the ADC core. The figure of merit is 0.42 pJ/conv. © 2011 IEEE.