Abstract
Over the last two decades, silicon CMOS scaling [1, 2] had been the foundation of the information revolution. It is worthwhile to realize that prior to 1990, CMOS was more of a density driver, and it was based on DRAM technology. Where performance was needed, one had to rely on bipolar or BiCMOS technologies. In early 90's the power of a number of high end bipolar chips approached ∼100 W/cm2 value, and the outlook for further bipolar technology performance improvement (constrained by power) was put in doubt. That forced an industry migration away from BiCMOS to scaled CMOS, based on Dennard's scaling theory [2]. Over the next 20 years, a new CMOS node, every two years, with 2X density shrink and ∼35% performance gain per technology node became the norm. Over the last few years, and starting at 90 nm, total chip power and power density have approached the air-cool limit of ∼100 W/cm 2. Furthermore, as we have moved to 65, 45 and the upcoming 32 nm nodes, scaling has deviated from the ideal theory (i.e. slowdown in drop in supply voltage and increase in leakage power). The combined effect of the above have been a halt in the frequency scaling for the chips with conventional cooling (around 4 GHz), and migration to multi-core systems (Figure 1). © 2009 IEEE.