Ruqiang Bao, K. Watanabe, et al.
VLSI Technology 2020
FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ∼8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.
Ruqiang Bao, K. Watanabe, et al.
VLSI Technology 2020
Veeraraghvan S. Basker, Theodorus E. Standaert, et al.
VLSI Technology 2010
Abhijeet Paul, Andres Bryant, et al.
IEDM 2013
Tian Shen, K. Watanabe, et al.
IRPS 2020