A 31 GHz CML ring VCO with 5.4 ps delay in a 0.12-μm SOI CMOS technology

Abstract

This paper presents a three-stage CML (current mode logic) ring VCO fabricated in a 0.12 μm SOI CMOS technology with a minimum stage delay of 5.4 ps at a differential voltage swing of 400 mV. The maximum oscillation frequency measured is 31 GHz. A tuning range as high as 10% is measured. The phase noise is -95.6 dBc at an offset frequency of 10 MHz. The energy per stage is as low as 26.8 fJ at a power supply voltage of 1.5V and a delay per stage of 5.95 ps. © 2003 IEEE.