High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

Abstract

This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 μm SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH/μm2 is obtained for a 42 nH MTS (Multi-turn, multiple metal layers in Series) inductor.