500 MHz 32-word×64-bit 8-port self-resetting CMOS register file and associated dynamic-to-static latch

Abstract

A high performance multiport register file was designed and operated employing self-resetting CMOS(SRCMOS). The register file is tolerant to a very wide range of input pulsewidths but delivers tightly controlled outputs. In addition, SRCMOS dynamic-to-static conversion latch that enables the register file to be compatible with either dynamic or static dataflows is demonstrated.